The present invention relates generally to a thyristor, and more particularly, to a thyristor having increased tolerance to overvoltage.
The features of the present invention are hereunder described with particular reference to p-gate thyristors, a typical example of which is shown in cross-section in FIG. 1. In this figure, an n-type semiconductor substrate forms an n-type base layer 1 (hereafter referred to as an n.sub.B layer). A p-type base layer 2 (hereafter called the p.sub.B layer) is formed on the upper surface of the n.sub.B layer 1. A p-type emitter layer 3 (hereafter called the p.sub.E layer) is formed on the lower surface of the n.sub.B layer 1. An n-type emitter layer 4 (hereafter called the n.sub.E layer) is formed on the upper surface of the p.sub.B layer 2 so as to partially surround it. A p-type gate region 5 results from that part of the surface p.sub.B layer 2 which is surrounded by the n.sub.E layer 4. An anode 6 is formed on the lower surface of the p.sub.E layer 3 and a cathode 7 is formed on the surface of the n.sub.E layer 4. A gate electrode 8 is formed on the surface of the p-type gate region 5. A bevel 9 is made around the edges of the p.sub.E layer 3, the n.sub.B layer 1, the p.sub.B layer 2, and the n.sub.E layer 4 so as to reduce the surface electric field. A surface stabilizing film 10 is made to adhere to the bevel 9. A p-n junction J.sub.1 is formed between the n.sub.B layer 1 and the p.sub.E layer 3; a p-n junction J.sub.2 is formed between the n.sub.B layer 1 and the p.sub.B layer 2; and a p-n junction J.sub.3 is formed between the p.sub.B layer 2 and the n.sub.E layer 4.
With the thyristor having the construction shown in FIG. 1, the allowable reverse bias is determined by the tolerance of the p-n junction J.sub.1 and the allowable forward bias is determined by the tolerance of p-n junction J.sub.2. The tolerable bias across these two junctions is determined by the impurity concentration N of the n.sub.B layer 1 and the thickness W.sub.nB of the n.sub.B layer 1. If J.sub.1 and J.sub.2 are each step junctions, the tolerable voltage V.sub.Bo is given by 5.6.times.10.sup.13 N.sup.-3/4 when the tolerable voltage is determined by avalanche breakdown. If a reverse bias V.sub.Bo is applied to each junction, the spread of the depletion layer W is given by 3.62.times.V.sup.1/2 .times.N.sup.-1/2.
In most thyristors, the n.sub.B layer 1 is made of a single crystal silicon wafer fabricated by the floating zone (FZ) process. An example of the specific resistivity distribution of the FZ water in the radial direction is shown in FIG. 2, wherein the horizontal axis plots the radial location of a certain area as measured from the periphery of the wafer and the vertical axis shows the specific resistivity (in ohm-cm) of that area. Since the specific resistivity is virtually in inverse proprotion to the impurity concentration, the specific resistivity distribution may well be regarded as indicating the distribution of the impurity concentration. In FIG. 2, (a) indicates the region having the highest impurity concentration and (b) represents the region having the lowest impurity concentration. Obviously, the variation in the impurity concentration of the FZ wafer is within .+-.15%.
In a conventional thyristor using an FZ wafer, the tolerable bias V.sub.Bo is the tolerable bias V.sub.Bo(A) at the region (A) shown in FIG. 1 that corresponds to area (a) having the highest impurity concentration so that the tolerable bias V.sub.Bo is determined by the impurity concentration of that area. No punch-through will occur if the thickness W.sub.nB of the n.sub.B layer 1 is greater than the spread W at the bias V.sub.Bo(A) of the depletion layer in that part (not shown) of the n.sub.B layer 1 which corresponds to area (b) of the lowest impurity concentration. Therefore, the tolerable bias V.sub.Bo of the thyristor is determined by the avalanche breakdown voltage V.sub.Bo(A) at area (A) of the n.sub.B layer 1. Accordingly, if a forward overvoltage greater than V.sub.Bo(A) is applied to the conventional thyristor using the FZ wafer, a local current flows in area (A) of the n.sub.B layer 1 to turn on the thyristor. While the turned-on area spreads slowly, a hot spot occurs in area (A) and may nonetheless destroy the thyristor. The same phenomenon will occur if an overvoltage is applied in reverse direction. However, it has been difficult to increase the tolerance of the conventional thyristor against overvoltage because the location of the area (A) of the n.sub.B layer 1 having the highest impurity concentration is usually unknown.
An improved version of the FZ wafer is commercially available which is given a relatively uniform distribution of impurity concentrations by converting Si.sup.30 in an FZ wafer of high specific resistivity to P.sup.31 through exposure to neutron radiation through a nuclear reaction some of the silicon is converted to phosphorous which is an n-type dopant. Called an NTD FZ wafer, this device has a specific resistivity profile in a radial direction of the type shown in FIG. 3, wherein the horizontal and vertical axes plot the same parameters as in FIG. 2, and (a) indicates the area having the highest impurity concentration and (b) represents the area having the lowest impurity concentration. As illustrated in FIG. 3, the variation in the impurity concentration of the NTD FZ wafer is within .+-.5% and the distribution of the impurity concentrations in this wafer is more uniform than that of the FZ wafer shown in FIG. 2. Nevertheless, the location of the area (A) in the n.sub.B layer 1 of a thyristor using this wafer having the highest impurity concentration is not precisely known, and therefore increasing the tolerance of the thyristor is no less difficult than in the case of the thyristor using the conventional FZ wafer.